fix(backend): Registers can alloc, ret var and asm format
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@@ -43,7 +43,7 @@ pub const REGISTERS: &[Register] = &[
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];
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pub const REGISTERS_CAN_ALLOC: &[Register] = &[
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_R8, REG_R9, REG_R10, REG_R11, REG_R12
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REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, REG_R8, REG_R9, REG_R10, REG_R12
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];
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pub struct RegisterAlloc {
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allocator: Weak<RefCell<RegisterAllocatorInner>>,
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