feat(loader, kernel): impl part of loader and initialize kernel structure

arch/x86_64/desc.zig

@@ -0,0 +1,43 @@
+const processor = @import("processor.zig");
+
+pub const GateDesc = packed struct {
+    offset_1: u16 = 0,
+    selector: u16 = 0,
+    ist: u3 = 0,
+    _reserved_1: u5 = 0,
+    gate_type: GateType = .interrupt,
+    _padding: u1 = 0,
+    dpl: processor.PrivilegeLevel = .Kernel,
+    present: u1 = 0,
+    offset_2: u16 = 0,
+    offset_3: u32 = 0,
+    _reserved_2: u32 = 0,
+    pub const GateType = enum(u4) {
+        interrupt = 0xe,
+        trap = 0xf,
+    };
+    pub fn getOffset(self: *const GateDesc) u64 {
+        return (@as(u64, self.offset_3) << 32) | (@as(u64, self.offset_2) << 16) | self.offset_1;
+    }
+    pub fn setOffset(self: *GateDesc, offset: u64) void {
+        self.offset_1 = @as(u16, offset & 0xFFFF);
+        self.offset_2 = @as(u16, (offset >> 16) & 0xFFFF);
+        self.offset_3 = @as(u32, (offset >> 32) & 0xFFFFFFFF);
+    }
+};
+
+pub fn loadIdt(idt_table: []const GateDesc) void {
+    var idt_ptr: packed struct {
+        limit: u16,
+        base: u64,
+    } = .{
+        .limit = @as(u16, @sizeOf(GateDesc) * idt_table.len - 1),
+        .base = @intFromPtr(&idt_table[0]),
+    };
+    asm volatile (
+        \\ lidt %rax
+        :
+        : [idt_ptr] "{rax}" (&idt_ptr)
+        : .{}
+    );
+}